This invention relates to a boundary scan cell which can be applied to bi-directional terminals.
As a method of easily testing a semiconductor chip mounted on a board, boundary scan cells have been frequently used in recent years. FIG. 3 shows the configuration of a circuit in which conventional boundary scan cells SF1 to SF4 for bi-directional input/output terminals are arranged. There are provided a block of a logic circuit (hereinafter referred to as a logic block) BL1 having four bi-directional input/output terminals I011 to I014, a terminal PI1 exclusive for an external input, and a terminal PO1 exclusive for an external output, and a logic block BL2 having four bi-directional input/output terminals I021 to I024, a terminal PI2 exclusive for an external input, and a terminal P02 exclusive for an external output. The boundary scan cells SF1 to SF4 connect the two logic blocks BL1 and BL2 each other at the time of an ordinary operation. For example, the boundary scan cell SF1 connects the bi-directional input/output terminals IO11 and I021 through terminals D1 and D2. At the time of test, the boundary scan cell SF1 disconnects this connection, thus permitting testing of each block independently.
The details of the circuit configuration of such a boundary scan cell SF are shown in FIG. 4. Between the terminals D1 and D2, analog switches TG1 and TG2 are connected in series. A signal supplied to a terminal T1 controls the on/off operation of the analog switch TG1. Similarly a terminal T2 controls the analog switch TG2.
A test data input terminal SID to which test data is supplied is connected to a data terminal D of a flip-flop FF1, and a terminal G1 is connected to a clock terminal CLK. An input terminal of an output gate TBF, which is capable of tri-state output, is connected to a positive output terminal Q. The output terminal of the output gate TBF is connected to a node N1 connecting the analog switches TG1 and TG2 and to a data terminal D of a flip-flop FF2. A terminal G2 is connected to the clock terminal CLK of the flip-flop FF2, and a test data output terminal SOD is connected to the positive output terminal Q thereof.
A terminal SIM to which data is supplied is connected to a data terminal D of a flip-flop FF3, and a terminal G3 is connected to a clock terminal CLK. A data output terminal SOM is connected to a positive output terminal Q through a node N2. Further, input terminals of an AND/OR gate 11 comprised of AND circuits AN11 and AN12 and an OR circuit OR11 are respectively connected to terminals MODE1 and MODE2 which is used for mode setting, and an output terminal thereof is connected to the terminal for controlling the operation of the output gate TBF. The terminal MODE1 and an input of an inverter INV1 are connected to one input terminal of the AND circuit AN11. A node N2 is connected to the other input terminal of the AND circuit AN11, and one input terminal of the 0R circuit OR11 is connected to the output terminal thereof. Further, the terminal MODE2 which is used for mode setting is connected to one input terminal of the AND circuit AN12, an output terminal of the inverter INV1 being connected to the other input terminal thereof, and the other input terminal of the OR circuit OR11 is connected to the output terminal thereof. The output terminal of the OR circuit OR11 is connected to the enable terminal of the output gate TBF.
The conventional boundary scan cell explained above operates as follows. Description will be first given in connection with the case where the logic block carries out an ordinary operation. When the voltage level of the terminals of T1 and T2 are high level, the analog switches TG1 and TG2 are both turned ON. Further, when the terminals MODE1 and MODE2 are both low level, an output of low level is provided from the AND/OR gate 11 and is then applied to the output gate TBF. Thus, the output of the gate TBF becomes high impedance. As a result, the terminals D1 and D2 are connected to each other, consequently bi-directional data transmission between logic blocks BL1 and BL2 is possible.
When test of the logic block is carried out, the boundary scan cell operates as follows. The terminals T1 and T2 are both set at a low level. As a result, the analog switches TG1 and TG2 are both turned OFF in a manner opposite to that in the ordinary operating state. Setting of data which assigns input/output modes of corresponding bi-directional input/output terminals of a logic block to be tested is carried out by storing input/output setting data into the flip-flop FF3. Further, test vector data are stored in the flip-flops FF1 and FF2.
For example, when the logic block BL1 is tested, data which assigns input/output modes of corresponding terminals are set to H or L logic level depending on whether the terminals are input mode or output mode. Here, as shown in FIG. 3, input terminals SIM and output terminals SOM in the boundary scan cells SF1 to SF4 are connected in series, respectively. Accordingly, by supplying a clock signal to the terminals G3 of flip-flops FF3 of the boundary scan cells SF1 to SF4, it is possible to serially transfer input/output mode setting data into the flip-flops FF3. Data store in a flip-flop FF3 controls the output voltage level of gate TBF so that it is in a low impedance state where corresponding bi-directional input/output terminals of the logic block BL1 are in the input mode, and the output of gate TBF becomes high impedance state where those terminals are in the output mode.
While this input mode setting data is stored in FF3, the voltage level terminals MODE1 and MODE2 may be either high level or low level. This is because, even if the output impedance of the gate TBF is assumed to be low impedance, i.e. it is in an output enabling state, since the analog switches TG1 and TG2 are both in an OFF state, the levels of the terminals MODE1 and MODE2 have no influence on the internal states of the logic blocks BL1 and BL2. When storing the input/output mode setting data into the flip-flop FF3 is completed, supply of a clock signal to the terminal G3 is stopped.
Setting of test vector data into the flip-flop FF1 is then carried out. This setting is carried out by storing test vector data into the flip-flop FF1 using input terminal SID. The terminal MODE1 is set at a low level, and the terminal MODE2 is set at a high level. Thus, irrespective of the level of the positive output terminal Q of the, flip-flop FF3, output of the AND/OR gate 11 becomes high level. As a result, the output of gate TBF becomes low impedance, so it becomes output enable state. When the same clock signals are respectively supplied from the output terminals G1 and G2 to the flip-flops FF1 and FF2, the two flip-flops synchronously operate. Thus, test vector data is transferred from the input terminal SID to the output terminal SOD. As shown in FIG. 3, there results a state wherein flip-flops FF1 and FF2 of the respective boundary scan cells SF1 to SF4 are connected to each other in series. Thus, test data are set, respectively. When storing of the test data is completed, the supply of clock signals to the respective flip-flops FF1 and FF2 is stopped. Since the input/output setting data is stored in the flip-flop FF3, and test vector data is stored in the flip-flop FF1, data necessary for test are all stored in flip-flops. Thereafter, test of the logic block BL1 is carried out.
Next the terminals T1 and T2 are set to high level and low level, thus allowing the analog switches TG1 to be turned on and TG2 to be turned off, respectively. At the same time, the terminal MODE1 is set to be at high level, and the terminal MODE2 is set to be at high or low level. In the case where corresponding bi-directional input/output terminals of the logic block BL1 is in an input mode, the output of the output gate TBF becomes low impedance, so it is in an output enable state. As a result, test data stored in the flip-flop FF1 is supplied to corresponding bi-directional input/output terminals of the logic block BL1. In contrast, in the case where the bi-directional input/output terminals are in an output mode, the output gate TBF is set so that it is in a high impedance state. Then, a clock signal is supplied to the terminal G2. Thus, data indicative of a test result are output from the bi-directional input/output terminals of the logic block BL1 and stored in the flip-flop FF2.
Thereafter, the terminal T1 is set at a low level, turning analog switch TG1 OFF. By setting the terminals MODE1 and MODE2 to low level and high level respectively, a signal of high level is output from the AND/OR gate 11 irrespective of the output from flip-flip FF3. Thus, the output of the output gate TBF becomes low impedance state, resulting in an output enable state. When the same clock signals are respectively delivered to the terminals G1 and G2, the flip-flops FF1 and FF2 operate synchronously. Thus, data output from the logic block BL1 is transferred from the terminal SID to the terminal SOD. As a result, test results stored in the respective flip-flops FF2 of the boundary scan cells SF1 to SF4 are serially taken out to the outside.
As stated above, at the time of test mode, except in the case in which test data is input into the logic block BL1, or a test result is taken out therefrom, the analog switches TG1 and TG2 are turned OFF in order that there be no influence on the internal state of the logic block BL1. Thus, the logic block BL1 and the boundary scan cells are disconnected.
The conventional boundary scan cell has the following problem. As described above, in the test mode, except when transmission/reception of data is out between the boundary scan cell and the logic block, the analog switches TG1 and TG2 are in an OFF state, so that there is no influence on the internal state of the logic block. For the time period during which these analog switches TG1 and TG2 are in the OFF state holding of test data to be applied to the bi-directional input/output terminal, or holding of a test result taken out, is accomplished by a dynamic operation to hold charges in a parasitic capacitor on the node N3 connecting the terminal D1 and the analog switch TG1. Charges stored in the parasitic capacitor leak with the elapse of time and gradually decrease. The time required for holding such charges is generally about 50 us. Accordingly, there is established a restriction whereby setting of the input/output mode setting data or the test data must be completed within such an extremely short time. In addition, holding of data by the dynamic operation is apt to be the influenced by power supply noise etc., so sometimes data may change.